Level 17: Anatomy of a Decoder

Task

Build the recognition logic for 3 opcodes (ADD, STA, JMP) in the decoder. LED indicators on the outputs show which line is active.

The instruction decoder translates an instruction code into control signals. A FRAMEWORK is already on the canvas: - Splitter (pre:spl) — breaks the Instr input bus into 8 bits. - 4 NOT inverters: ~Bit0 (pre:not0), ~Bit1 (pre:not1), ~Bit2 (pre:not2), ~Bit3 (pre:not3).

Solution

The Instr input is a byte. Bits 4-7 hold the COMMAND (opcode): - ADD = 0001 (opcode 1, hex 0x10). - STA = 0110 (opcode 6, hex 0x60) — memory write. - JMP = 0111 (opcode 7, hex 0x70) — unconditional jump.

Your task: add AND gates to "recognize" these codes. Each opcode needs a chain of THREE ANDs (one AND takes only 2 inputs, but you need to check 4 bits).

═══════ STA (opcode 6 = 0110) → MemWr output ═══════ Must trigger when: Bit0=0, Bit1=1, Bit2=1, Bit3=0.

AND#1: input A = pre:not0 (~Bit0), input B = Splitter.Bit5 (Bit1 of opcode). AND#2: input A = AND#1 output, input B = Splitter.Bit6 (Bit2 of opcode). AND#3: input A = AND#2 output, input B = pre:not3 (~Bit3). Connect AND#3 output to MemWr.

═══════ JMP (opcode 7 = 0111) → JumpUncond output ═══════ Must trigger when: Bit0=1, Bit1=1, Bit2=1, Bit3=0.

AND#4: input A = Splitter.Bit4 (Bit0 of opcode), input B = Splitter.Bit5 (Bit1). AND#5: input A = AND#4 output, input B = Splitter.Bit6 (Bit2). AND#6: input A = AND#5 output, input B = pre:not3 (~Bit3). Connect AND#6 output to JumpUncond.

═══════ ADD (opcode 1 = 0001) ═══════ All outputs should be 0 — leave ALUOp0, ALUOp1, JumpCond unconnected. An unconnected Output always reads as 0.