Decoder (Instruction Decoder)
Inputs
| Pin | Type | Description |
|---|---|---|
| Instr | bus8 | Instruction byte — bits 7:4 = opcode, bits 3:0 = operand (ignored) |
Outputs
| Pin | Type | Description |
|---|---|---|
| ALUOp0 | bit | ALU operation select, bit 0 |
| ALUOp1 | bit | ALU operation select, bit 1 |
| MemWr | bit | Memory write enable (1 = write to RAM) |
| JumpUncond | bit | Unconditional jump to PC.Load |
| JumpCond | bit | Conditional jump (if Zero flag = 1) |
| RegLoad | bit | Load accumulator register |
| IXLoad | bit | Load index register (extended I/O addressing) |
| IXInc | bit | Increment index register |
| UseIX | bit | Use index register as memory address source |
How It Works
The Decoder is a combinational circuit that converts a 4-bit opcode into a set of 9 control signals. These signals orchestrate all CPU operations: ALU function selection, memory access, register control, and program flow.
Opcode → Control Signals table:
| Opcode | Mnemonic | ALUOp[1:0] | MemWr | JumpUncond | JumpCond | RegLoad | IXLoad | IXInc | UseIX |
|---|---|---|---|---|---|---|---|---|---|
| 0 | NOP | — | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | ADD | 00 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 2 | SUB | 01 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 3 | AND | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 4 | OR | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 5 | LDA | — | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 6 | STA | — | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 7 | JMP | — | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 8 | JZ | — | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 9 | LDX | — | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 10 | LDAX | — | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 11 | STAX | — | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 12 | JN | — | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 13 | INX | — | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 15 | HLT | — | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Key behaviors:
- HLT (opcode 15): all outputs are 0 — the CPU stops clocking.
- ALU operations (1–4): RegLoad = 1 to store the result in the accumulator. ALUOp selects the operation.
- Jumps (7, 8, 12): JumpUncond for JMP, JumpCond for JZ/JN (conditional on Zero/Negative flag).
- Index register (9–13): LDX, LDAX, STAX, INX use the IX register for extended memory addressing (enables access to I/O ports 0xE0–0xFF).
See the Assembler Manual for the full instruction set reference.
Usage
The Decoder is essential for CPU operation:
- Level 17: build the Decoder from basic gates (NOT, AND, OR).
- Level 18: use the pre-built Decoder component to complete the CPU.
In a complete CPU:
- Instr connects to the output of the instruction ROM (via a Splitter that extracts bits 7:4).
- Control outputs connect to target components: ALUOp to ALU8, MemWr to RAM WE, JumpUncond/JumpCond to PC Load, RegLoad to Register8, IXLoad/IXInc/UseIX to the Index Register and MUX selectors.
Without the Decoder, instructions have no effect — the CPU cannot interpret opcodes.