DFF (D Flip-Flop)
Inputs
| Pin | Type | Description |
|---|---|---|
| D | bit | Data input — the bit to store |
| Clock | bit | Clock signal — write on 0→1 edge |
Outputs
| Pin | Type | Description |
|---|---|---|
| Q | bit | Stored value (output) |
How It Works
The D (Data) input value is captured and stored on the rising edge of the Clock signal (transition from 0 to 1). Between clock edges, Q holds the previously captured value regardless of changes on D.
The DFF is a sequential node (tcSequential flag). This means its output is not updated immediately during the simulation pass — it is computed in phase 1 and atomically committed in phase 2 of the three-phase solver. This prevents glitches and race conditions in clocked circuits.
Usage
Featured in level 11. The DFF is the fundamental building block of sequential logic — memory. It is the simplest clocked storage element.
Eight DFFs placed in parallel, sharing a common Clock and each receiving one bit of an 8-bit bus, form an 8-bit register. This is exactly what the Register8 component does internally.