RAM (256 bytes)
Inputs
| Pin | Type | Description |
|---|---|---|
| Addr | bus8 | Memory address (0–255) |
| DataIn | bus8 | Data to write (8 bits) |
| WE | bit | Write Enable: 1 = write DataIn at Addr |
Outputs
| Pin | Type | Description |
|---|---|---|
| DataOut | bus8 | Value read from address Addr |
How It Works
If WE = 1: the DataIn value is written to memory cell at address Addr. Then (after the write) DataOut reflects the value at Addr — which is now the newly written value.
If WE = 0: DataOut shows the value at Addr without modification.
All 256 cells are initialized to 0 at the start of simulation. Memory contents are lost when the page is reloaded (no persistence).
Usage
Serves as data memory in Harvard architecture (levels 18, 20–22, 25–29). Stores variables, arrays, and computation results.
Addressing: the instruction operand (lower 4 bits, values 0–15) selects the RAM address for LDA/STA/ADD/SUB/AND/OR instructions. Only addresses 0–15 are directly addressable by instructions. Cells 16–255 are accessible only via the IndexRegister (IX) with LDAX/STAX indirect addressing, or via the browser console for debugging.