Level 11: Smart memory

Task

Build a D flip-flop (DFF). Data is captured on the rising edge of the Clock.

A D flip-flop (DFF) captures the value on input D at the RISING EDGE of the Clock signal (the moment it transitions from 0 to 1).

Solution

Built using master-slave configuration from four NAND gates:

1. NAND#1: inputs A=D (data), B=Clock. 2. NAND#2: inputs A=NAND#1 output, B=Clock. 3. NAND#3: inputs A=NAND#1 output, B=NAND#4 output. 4. NAND#4: inputs A=NAND#2 output, B=NAND#3 output.

The first pair (NAND#1+#2 = master) accepts data when Clock=1. The second pair (NAND#3+#4 = slave) stores when Clock=0.

NAND#3 output (Q) is the main output. Connect Clock from the pre-placed Clock element (pre:Clock) on the canvas.